FPGA-based Accelerators for Parallel Data Sort

The paper is dedicated to parallel data sort based on sorting networks. The proposed methods and circuits have the following characteristics: 1) using two-level parallel comparators in even-odd transition networks with feedback to a register keeping input/intermediate data; 2) parallel merging of many sorted sequences; 3) using even-odd transition networks built from other sorting networks; 4) rational reuse of comparators in different types of networks, namely even-odd transition and for discovering maximum/minimum values. The experiments in FPGA, which were done for up to 16×2 32-bit data items, demonstrate very good results (as fast as 3-5 ns per data item).